This invention relates to programmable logic array integrated circuit devices, and more particularly to improved carry chain circuitry for use in such devices.
Cliff et al. U.S. Pat. No. 5,274,581 (which is hereby incorporated reference herein) shows circuitry which is suitable for use as a basic logic module in a programmable logic array integrated circuit device. Among the many possible logic functions this circuitry can perform, some special features are included to facilitate use of the circuitry to perform one place of binary addition. This includes accepting two addend bits and a carry in bit (from the logic module performing the next lower order place of the addition) and producing a sum out bit and a carry out bit (for application as a carry in bit to the logic module performing the next higher order place of the addition). (Although for the most part only adders and addition are discussed in detail herein, it will be appreciated that adders are at the heart of other possible uses of this logic module circuitry. Among these other possible uses are subtraction and many different kinds of counters (e.g., up counters, down counters, loadable counters, resettable counters, etc.). This is discussed in more detail in the '581 patent. References to adders, addition, or the like herein will be understood to also include these various other possible uses of the apparatus.)
The '581 patent shows the carry out terminal of each logic module being "hard wired" to the carry in terminal of another (usually adjacent) logic module so that the logic modules are arranged in a fixed order in a carry chain. Thus if one wishes to use the carry chain circuitry, the fixed order of the logic modules along the carry chain dictates the arithmetic place that each logic module must perform. This restriction can reduce the overall usability of the programmable logic array device. For example, as a result of other logic which must be placed on the device, it may be found that only certain groups of logic modules have the connectivity required to receive the addend bits in the required order and to produce the sum out bits also in the required order. Or it may be found that in order to place an adder in the particular group of logic modules that has the proper connectivity for the addend and sum out bits, it is not possible to place on the device other logic that is needed.
In view of the foregoing, it is an object of this invention to provide improved programmable logic array integrated circuit devices.
It is a more particular object of this invention to provide improved carry chain circuitry for programmable logic array integrated circuit devices.